`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/12/17 20:50:23
// Design Name: 
// Module Name: tb_pll
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_pll();


real vco_phase;
real vco_phase_io;
real pfd_phase;
reg clk,clk1;
reg resetn;
wire signed [6:0] minus_1;
integer file;

    
real divider;
test_pll pll_1(
.resetn (resetn),
.clk    (clk),
.vco_phase  (vco_phase),
.vco_phase_io (vco_phase_io),
.pfd_phase  (pfd_phase),
.minus_1    (minus_1)
);

divider divider1(
.clk        (clk),
.resetn     (resetn),
.minus_1    (minus_1)
);

assign  pfd_phase = vco_phase/32; 

real ave,sum;
real i;
always@(posedge clk or negedge resetn) begin
        if(!resetn) begin
         ave<=0;
         sum<=0;
         i<=0;
        end
        else begin
            sum=sum+minus_1;
            i=i+1.0;
            ave=sum/i;
            $fwrite(file,"%f\n",minus_1);
        end
    end
            
            
       
    

initial begin
    resetn=0;

//    minus_1=0;
    #1000  resetn=1;
file=$fopen("dsm.csv");
//    #400 minus_1=-3;
//    #400 minus_1=-2;
//    #400 minus_1=-1;
//    #400 minus_1=-0;
//    #400 minus_1=1;
//    #400 minus_1=2;
//    #400 minus_1=3;
//    #4000 minus_1=0;
    
    
end


endmodule
